Semiconductor device

ABSTRACT

A semiconductor device has a least one logic circuit and at least one memory macro cell having a plurality of memory cell array blocks each composed of a plurality of memory cells. Addresses for designating the memory cell array blocks in test are selected among external addresses by a switching signal. The semiconductor device may have a plurality of memory macro calls having a plurality of memory cell array blocks each composed of a plurality of memory cells. The memory macro cells are switched in configuration as having the same length of rows or columns between the memory macro cells in test. The configuration is different from a configuration of row and column for a regular operation.

CROSS REFERENCE TO RELATED APPLICATIONS

[0001] The subject application is related to subject matter disclosed inJapanese Patent Application No. H 11-317887 filed on Nov. 9, 1999 inJapan to which the subject application claims priority under ParisConvention and which is incorporated herein by reference.

BACKGROUND OF THE INVENTION

[0002] The present invention relates to a semiconductor device havingmemory circuits.

[0003] Memory-logic LSIs (system LSIs) have been popular recently. TheseLSIs are used to constitute a specific system by mounting memorycircuits and logic circuits on one chip. Circuits that are usuallymounted on separate chips are mounted on one chip for memory-logic LSIs,thus requiring higher performance, lower power consumption andminiaturization (reduction of components).

[0004] There are two types for memory-logic LSIs. One is a custom LSIhaving custom logic and memory circuits. The other type is a ASIC(Application Specific IC) that is a semi-custom LSI having memorycircuits ( memory macro cells) designed as function blocks.

[0005] ASICs are very popular for their flexibility to a variety ofusers' demands because they can be rearranged in a short turn aroundtime.

[0006] As memory macro cells for ASICs, re-configurable memory macrocells have been developed.

[0007] Re-configurable memory macro cells are, however, disadvantageousin high cost for testing each macro cell due to different test programsfor a plurality of different types of products using memory macro cellsconfigured differently.

[0008] Moreover, memory macro cells cannot be tested at the same timedue to different address spaces for a plurality of memory macro cellsmounted on a one-chip memory-logic LSI.

SUMMARY OF THE INVENTION

[0009] A purpose f the present invention is to provide a LSI havingre-configurable memory circuits with a low cost for memory testing andalso switching in performance specifications.

[0010] The present invention provides a semiconductor device including;at least one logic circuit; and at least one memory macro call having aplurality of memory cell array blocks each composed of a plurality ofmemory cells, wherein addresses for designating the memory cell arrayblocks in test are selected among external addresses by a switchingsignal.

[0011] Moreover, the present invention provides a semiconductor deviceincluding: at least one logic circuit: and a plurality of memory macrocalls having a plurality of memory cell array blocks each composed of aplurality of memory cells wherein at least one of the memory macro cellsis switched in configuration as having the same length of rows orcolumns between the memory cell array blocks in test the configurationbeing different from a configuration of row and column for a regularoperation.

[0012] Furthermore, the present invention provides a semiconductordevice having a plurality of memory macro cells, each memory macro cellincluding: a plurality of memory cell array blocks each having aplurality of memory cells, composed of rows and columns; a decoderconfigured to decode a row or a column address signal to select at leastone memory cell located on a row or a column corresponding to thedecoded address signal; and a switching circuit configured to convertthe row or the column address signal in response to a switching signaland supply the converted signal to the decoder to set address spaceshaving the same number of rows or columns between the plurality ofmemory cells.

[0013] Moreover, the present invention provides a method of testing asemiconductor device having at: least one logic circuit and at least onememory macro cell having a plurality of memory cell array blocks eachcomposed of a plurality of memory cells, including the step of selectingaddresses for designating the memory cell array blocks among externaladdresses by a switching signal.

[0014] Furthermore, the present invention provides a method of testing asemiconductor device having at least one logic circuit and a pluralityof memory macro cells having a plurality of memory cell array blockseach composed of a plurality of memory cells, including the step ofswitching at least one of the memory macro cells in configuration ashaving the same length of rows or columns between the memory macrocells, the configuration being different from a configuration of row andcolumn for a regular operation.

BRIEF DESCRIPTION OF DRAWINGS

[0015]FIG. 1A shows one configuration of a memory macro cell used for amemory-logic LSI on which memory and logic circuits are mounted as apreferred embodiment according to the present invention;

[0016]FIG. 1B illustrates address allocation to the memory macro cellconfigured an shown in FIGS. 1A;

[0017]FIG. 2A shows another configuration of the memory macro cell shownin FIG. 1;

[0018]FIG. 2B illustrates address allocation to the memory macro cellconfigured as shown in FIGS. 2A;

[0019]FIG. 3 shows a block diagram of a row-side configuration-switchingcircuit and a row decoder shown in FIGS. 1A and 2A;

[0020]FIG. 4 shows a block diagram of a column-sideconfiguration-switching circuit 5 b and a column decoder shown in FIGS.1A and 2A;

[0021]FIG. 5 shows a circuit diagram of multiplexers shown in FIG. 4;

[0022]FIGS. 6A to 6C illustrate configurations of memory macro callsinstalled in different products;

[0023]FIGS. 7A to 7C illustrate configurations changed from those shownin FIGS. 6A to 6C;

[0024]FIGS. 8A to 8C illustrate different configurations changed fromthose shown in FIGS. 6A to 6C;

[0025]FIG. 9 illustrates three memory macro cells installed on one chipfor a particular type of system LSI as another preferred embodimentaccording to the present invention;

[0026]FIGS. 10A and 10B illustrate different configurations changed fromthose shown in FIGS. 9;

[0027]FIG. 11 shows circuit diagrams of a column-sideconfiguration-switching circuit and a column decoder in the embodimentshown in FIG. 9; and

[0028]FIG. 12 shows a modification to the configuration-switchingcircuit shown in FIG. 11.

DETAILED DESCRIPTION OF PREFERRED EMBODIMENT

[0029] Preferred embodiments according to the present invention will bedisclosed with reference to the attached drawings.

Embodiment 1

[0030]FIG. 1A shows one configuration of a memory macro cell 1 used fora memory-logic LSI on which memory and logic circuits are mounted. FIG.2A shows another configuration of the memory macro cell 1. FIGS. 1B and2B illustrate address allocation to the memory macro cell 1 configuredas shown in FIGS. 1A and 2A, respectively.

[0031] An input configuration indication signal CONF is at a level “0”in FIG. 1A whereas it is “1” in FIG. 2A.

[0032] The memory macro cell 1 has a 64 k-bit storage capacity in thisembodiment. The 64 k bits are configured as 4 k bits in row and 16 bitsin column in FIG. 1A whereas 1 k bits in row and 64 bits in column inFIG. 2A. These configurations are switched by the signal CONF accordingto its level “0” or “1”.

[0033] The memory macro cell 1 in this embodiment is a DRAM having amemory cell array 2 in which each memory cell MC is provided at theintersection of a word line WL and a column selection line CSL a rowdecoder 3 for word line selection, and a column decoders 4 a and 4 b forselection of the column selection line.

[0034] Data can be written to and read from memory cells MC according toexternally input row addresses RA [0:113] and column addresses [0:5].

[0035] The row addresses RA [0:11] and column addresses CA, 0:5] areinput to configuration-switching circuits 5 a: and 5 b, respectively..These circuits decide whether or not to use all of the row addresses RA[0:11] and column addresses CA [0:5].

[0036] In FIG. 1A, a “0”-CONF signal is supplied to theconfiguration-switching circuit 5 a to validate all the row address s RA[0:11]. The row addresses RA [0:11] are converted into internal rowaddress a RAINT [0:11] and supplied to the row decoder 3. The rowdecoder 3 activates word lin s WL corresponding to the internal rowaddresses RAINT [0:11]. In other words, a word line/4 k bits isactivated for each of the 12-bit internal row addresses RAINT [0:11].

[0037] The “0”-CONF signal is also supplied to theconfiguration-switching circuit 5 b to invalidate the upper 2 bits ofthe column addresses CA [0:5]. The column addresses CA [0:5] are thusconverted into internal column addresses CAINT [0:3] and supplied to thecolumn decoder 4 a. The column decoder 4 a activates column selectionlines CSL corresponding to the internal column addresses CAINT [0:3].

[0038] The other column decoder 4 b is used for internal addresses CA[4:5] that are required when some of the rows in the direction X are notallocated row addresses. In FIGS. 1A and 1B, however, the column decoder4 b is not used due to invalidation of the internal addresses CA [4:5]in this embodiment.

[0039] In FIG. 2A, a “1”-CONF signal is supplied to theconfiguration-switching circuit 5 a to invalidate the upper two bits ofthe row addresses RA [0:11]. The row addresses RA [0:11] are thusconverted into internal row addresses RAINT [0:9] and supplied to therow decoder 3. The row decoder 3 activates word lines WL correspondingto the internal row addresses RAINT [0:9]. In other words, a word line/1k bits is activated for each of the 10-bit internal row addresses RAINT[0:9].

[0040] The “1”-CONF signal is also supplied to theconfiguration-switching circuit 5 b to validate all the column addressesCA [0:5]. The column addresses CA [0:5] are converted into internalcolumn addresses CAINT [0:5]. The lower 4 bits of the internal columnaddresses CAINT [0:5] are supplied to the column decoder 4 a whereas theupper 2 bits are supplied to the column decoder 4 b. The column decoder4 a activates column selection lines CSL corresponding to internalcolumn addresses CAINT [0:3]. The column decoder 4 b activates columnselection lines CSL corresponding to internal column addresses CAINT[4:5].

[0041] As disclosed, in response to the “0”-CONF signal, the memorymacro cell 1 is addr ssed with the row addresses RA [0:11] and thecolumn addresses CA [0:3] to configure a 4 k-row×16-column memory cell,as shown in FIGS. 1A and 1B.

[0042] On the other hand, in response to the “1”-CONF signal, the memorymacro cell 1 is addressed with the row addresses RA [0:9] and the columnaddresses CA [0:5] to configure a 1 k-row×64-column memory cell, asshown in FIGS. 2A and 2B.

[0043] As disclosed above, the memory macro cell according to thepresent invention is equipped with configuration-switching circuits forchanging the configuration of the memory cell array in response to aconfiguration indication signal CONF.

[0044] Therefore, the present invention achieves the same test for aplurality of memory macro cells by changing the configuration of theirmemory cell arrays into the same configuration even though the cellswill be used for different LSI types.

[0045] Changing the configuration of the memory cell arrays of thememory macro cells according to the present invention into a 1 k-rowconfiguration is one of the preferable ways for conducting the same testto the memory macro cells installed in different types of LSI. Forexample, the memory macro cell shown in FIGS. 1A and 1B installed in aone type of LSI can be changed to that shown in FIGS. 2A and 2B to atest conducted for a plurality of memory macro calls.

[0046]FIG. 3 shows a block diagram of the configuration-switchingcircuit 5 a and the row decoder 3 shown in FIGS. 1A and 2A.

[0047] The configuration-switching circuit 5 a shown in FIG. 3 is a rowaddress-switching circuit equipped with four multiplexers 51 a to 51 dand two inverters 52 a and 52 b.

[0048] The configuration-switching circuit 5 a makes valid or invalidthe upper two-bit row addresses [10:11] to obtain complementary internalrow addresses RAINTt [10:11] and RAINTc [10:11].

[0049] The multiplexers 51 a to 51 d have a switch terminal “S”, a firstinput terminal “0” and a second input ten al “1” and an output terminal“O”. Either of the first or the second terminal is connected to theoutput terminal in response to a configuration indication signal CONFsupplied to the switch terminal.

[0050] In detail, row addresses RA [11] and RA [10] are supplied to thefirst input terminals “0” of the multiplexers 51 a and 51 c,respectively.

[0051] The row address RA [11] is further inverted by the inverter 52 aand supplied to the first input terminal “0” of the multiplexer 51 b.The row address RA [13] is further inverted by the inverter 52 b andsupplied to the first input terminal “0” of the multiplexer 51 d.

[0052] A supply voltage Vcc is fed to the second input terminal. “1” ofthe multiplexers 51 a to 51 d.

[0053] The row decoder 3 is equipped with AND gates G0 to G3 for 1 k-rowSelection and decoders RD0 to RD3 for cell selection in a 1 k row.

[0054] All the combinations of the internal row addresses RAINTt [10:11]and RAINTc [10:11] are supplied to the AND gates G0 to G3 to generate a1 k-row selection signal 1KR_SEL [0]. 1KR_SEL [1]. 1KR_SEL [2] or1KR_SEL [3].

[0055] The lower row addresses RA [0:9] are directly supplied to thedecoders RD0 to RD3 without passing through the configuration-switchingcircuit 5 a. One of the 1 k-row selection signals 1KR_SEL [0] to 1KR_SEL[3] supplied to the corresponding decoder RD0, RD1, RD2 or RD3 activatesa word line in the corresponding 1 k-row block 20, 21, 22 or 23 inresponse to one of the row addresses RA [0:9].

[0056] A “0”-CONF signal supplied to the input terminal “S” of themultiplexer 51 a lowers the level of the terminal “S” to low to bringthe row address RA [11] into the internal row address RAINTt [11].

[0057] On the other hand, the “0”-CONF signal supplied to the inputterminal “S” of the multiplexer 51 b via the inverter 52 a raises thelevel of the terminal “S” to high to bring the row address RA [11] intothe inverted internal row address RAINTc [11].

[0058] Likewise, the 0″-CONF signal is supplied to the multiplexers 51 cand 51 d obtain complementary internal row addresses [10] and RAINTc[10] corresponding to the row address RA [10].

[0059] For example, row addresses [10] and [11] at high and low levels,respectively, provides a high-level internal row addr ss RAINTt [10], alow-level internal row address RAINTc [10], a low-level internal rowaddress RAINTt [11] and a high-level internal row address RAINTc [11].

[0060] The combination of these addresses brings the output of the ANDgate G1 into high whereas low for the outputs of the AND gates G0, G2and G3. This produces a high-level 1KR SEL [1] selection signal only toactivate a word line in the block 21 among the 1 k-row blocks 20 to 23.

[0061] As disclosed above, the “0”-CONF signal activates 1 k-row blockcorresponding to one of the external row addresses RA [10:11] to changethe memory macro cell 1 into a 4 k-row memory cell, as shown in FIGS. 1Aand 1B.

[0062] On the other hand, a “1”-CONF signal forces all the multiplexers51 a to 51 d to output the supply voltage Vcc to invalidate the rowaddresses RA [10:11]. This brings all the internal row addresses RAINTt[10:11] and RAINTc [10:11] into high for the AND gates G0 to G3, thusgenerating high-level signals 1KR_SEL [0] to [3]. The high-level signalsactivate the word lines of the all the 1 k-row blocks 20 to 23 to changethe memory macro cell 1 into a 1 k-row memory cell, as shown in FIGS. 2Aand 2B.

[0063]FIG. 4 shows a block diagram of the configuration-switchingcircuit 5 b and the column decoder 4 b shown in FIGS. 1A and 2A.

[0064] The configuration-switching circuit 5 b shown in FIG. 4 is acolumn address-switching circuit equipped with four multiplexers 53 a to53 d and two inverters 54 a and 54 b.

[0065] The configuration-switching circuit 5 b makes valid or invalidthe upper two-bit column addresses CA [4:5] to obtain complementaryinternal column addresses CAINTt [4:5] and CAINTc [4:5].

[0066] The multiplexers 53 a to 53 d have a switch terminal “S”, a firstinput terminal “0” and a second input terminal “1” and an outputterminal “O”. Either of the first or the second terminal is connected tothe output terminal in response to a configuration indication signalCONF supplied to the switch terminal.

[0067] In detail, column addresses CA [5] and CA [4] are supplied to thefirst input terminals “0” of the multiplexers 53 a and 53 c,respectively.

[0068] The column address RA [5] is further inverted by the inverter 54a and supplied to the first input terminal “0” of the multiplexer 53 b.The column address CA [4] is further inverted by the inverter 54 b andsupplied to the first input terminal “0” of the multiplexer 53 d.

[0069] A supply voltage Vcc is fed to the second input terminals “1” ofthe multiplexers 53 a to 53 d.

[0070] The column decoder 4 b is equipped with AND gates G10 to G13 for1 k-row selection.

[0071] All the combinations of the internal column addresses CAINTt[4:5] and CAINTc [4:5] are supplied to the AND gates G10 to G13 togenerate a 1 k-row selection signal 1KC_SEL [0]. 1KC_SEL [1], 1KC_SEL[2] or 1KC_SEL [3].

[0072] The lower column addresses CA[0:3] are directly supplied to theother column decoder 4 a without passing through theconfiguration-switching circuit 5 b. One of the 1 k-row selectionsignals 1KC_SEL [0] to 1KC_SEL [3] activates a word line in thecorresponding 1 k-row block 20, 21, 22 or 23 in response to one of thecolumn addresses CA [0:3].

[0073] A “1”-CONF signal supplied to the input terminal “S” of themultiplexer 53 a raises the level of the terminal “S” to high to bringthe column address CA [5] into the internal column address CAINTt [5].

[0074] On the other hand, the “1”-CONF signal supplied to the inputterminal “S” of the multiplexer 53 b via the inverter 54 a lowers thelevel of the terminal “S” to low to bring the column address CA [5] intothe inverted internal column address CAINTc [5].

[0075] Likewise, the “1”-CONF signal is supplied to the multiplexers 53c and 53 d obtain complementary internal column addresses CAINTt [4] andCAINTc [4] corresponding to the column address RA [4].

[0076] For example, column addresses CA [4] and [5] at high and lowlevels, respectively, provides a high-level internal column addressCAINTt [4], a low-level internal column address CAINTc [4], a low-levelinternal column address CAINTt [5] and a high-level internal columnaddress CAINTc [5].

[0077] The combination of these addresses brings the output of the ANDgate G11 into high whereas low for the outputs of the AND gates G11, G12and G13. This produces a high-level 1KC_SEL [1] selection signal only toactivate a column line CSL in the block 21 among the 1 k-row blocks 20to 23.

[0078] As disclosed above, the “1”-CONF signal activates 1 k-row blockcorresponding to one of the external column addresses RA [4:5] to changethe memory macro cell 1 into a 64-column memory cell, as shown in FIGS.2A and 2B.

[0079] On the other hand, a “0”-CONF signal forces all the multiplexers53 a to 53 d to output the supply voltage Vcc to invalidate the columnaddresses CA [4:5]. This brings all the internal column addresses CAINTt[4:5] and CAINTc [4:5] into high for the AND gates G10 to G13, thusgenerating high-level signals 1KC_SEL [0] to [3]. The high-level signalsactivate the word lines of the all the 1 k-row blocks 20 to 23 to changethe memory macro cell 1 into a 16-column memory cell, as shown in FIGS.1A and 1B.

[0080] A circuit diagram shown in FIG. 5 is an example of themultiplxers 53 a to 53 d shown in FIG. 4.

[0081] A multiplexer shown in FIG. 5 is equipped with an inverter I1,AND gates G51 and G52, a NOR gate G53 and an inverter I2. The firstinput terminal “0” and the input terminal “S”, and the second inputterminal “1”, such as, those shown in FIG, 4, are connected to the ANDgates G51 and G52, respectively. Data input to the terminal “S” isdirectly supplied to the AND gate G51 and further inverted by theinverter I1 and supplied to the AND gate G52. The output of the two ANDgates are supplied to the NOR gate G53 and inverted by the inverter I2.

[0082] A high-level signal supplied to the input terminal “S” allows aninput signal to the first input terminal “0” to be output from theinverter I2 (output terminal “O”). On the other hand, a low-level signalsupplied to the input terminal “S” allows an input signal to the secondinput terminal “1” to be output from the inverter I2.

[0083] Although not shown, for the multipliers 51 a to 51 d shown inFIG. 3. th first input terminal “0” and the second input terminal “1”connected to the AND gates G51 and G52, respectively, are inverted.

[0084] In this case, a low-level signal supplied to the input terminal“S” allows an input signal to the first input terminal “0” to be outputfrom the inverter I2 (output terminal “O”). On the other hand, ahigh-level signal supplied to the input terminal “S” allows an inputsignal to the second input terminal “1” to be output from the inverterI2.

[0085] As disclosed above, the 64 k-memory macro cell according to thepreferred embodiment is changeable between configurations havingdifferent row-column ratios in response to a configuration-switchingsignal CONF.

[0086] It is thus achieved that, for ale, a 64 k-memory macro cell istested as having a (4 k-row×16-column) configuration for installation ona particular system LSI and is changed into a (3 k-row×64-column)configuration for a test which is conducted for every 64 K-memory macrocell with no consideration of LSI types.

[0087] Therefore, a plurality of memory macro cells according to thepresent invention in a 1 k-row configuration allows a test having thesame test program common to every memory macro cell.

[0088] The present invention is disclosed more in detail with aplurality of memory macro cells.

[0089]FIGS. 6A to 6C illustrate configurations of memory macro cellsaccording to the present invention installed in different LSI types.

[0090] Illustrated in FIGS. 6A, 6B and 6C are a (1 K-row×4 K-column)4M-memory macro cell, a (4 K-row×2 K-column) 8M-memory macro cell and a(2 K-row×8 K-column) 16M-memory macro cell, respectively, for respectiveLSI types.

[0091] Each memory cell is tested as it is with no configurationchanging for a particular LSI type on which the memory cell will beinstalled.

[0092] On the contrary, the memory cells are changed into configurationshaving 1 k-row addresses as illustrated in FIGS. 7A to 7C by means of aconfiguration-switching signal CONF for a test common to every memorymacro cell.

[0093] In FIG. 7A, the 4M-memory macro cell has no change inconfiguration from that shown in FIG. 6A.

[0094] In FIG. 7B, the 8M-memory macro cell is changed into a (1 K-raw×8K-column) configuration from the (4 K-row×2 K-column) configurationshown in FIG. 6B.

[0095] In FIG. 7C, the 16M-memory macro cell is changed into a (1K-row×16 K-column) configuration from the (2 K-row×8 K-column)configuration shown in FIG. 6C.

[0096]FIGS. 8A to 8C illustrate 2 K-culumn configurations changed from 4K-, 2 K- and 8 K-column configurations shown in FIGS. 6A to 6C,respectively.

[0097] The same row capacity-configuration as illustrated in FIGS. 7A to7C and 8A to 8C allows the sane test program, failed bit map-template,and so on, thus reducing a cost for testing.

Embodiment 2

[0098]FIG. 9 illustrates three memory macro cells installed on one chipfor a particular type of system LSI.

[0099] Memory macro cells M1, M2 and M3 are a 64 K-bit (4K-row×16-column)-, a 32 K-bit (1 K-row×32-column)- and a 16 K-bit(1-row×16-column)-memory macro cell, respectively. One column of thememory macro cell M2 corresponds to two I/Os. The Memory macro cells M1,M2 and M3 have configuration-changing circuits 81 to 83, respectivelycorresponding to the column configuration-changing circuit 5 b shown inFIG. 1.

[0100]FIG. 10A illustrates address allocation to the memory macro cellsM1 to M3 shown in FIG. 9. The memory macro cells are continuouslyaccessible with increase in external addresses as if they constitute onememory macro cell. FIG. 10B illustrates the configurations of the memorymacro cells M1, M2 and M3 for regular access. In FIG. 10B, the addressallocation to the memory macro cell M1 only has been changed like theEmbodiment 1.

[0101] The configuration illustrated in FIG. 10A is attained as follows:

[0102] The (4 K-rows 16-column) configuration of the memory macro cellM1 is changed into a (1 K-row×64-column) configuration by means f aconfiguration indication signal CONF supplied to the column configuratin-changing circuit 81 (FIG. 9) with column address allocation from 0 to63.

[0103] For the memory macro cell M2, the column addresses CA are shiftedby 64 and the column addresses 64 to 95 are allocated for two I/Os percolumn by the column configuration-changing circuit 82 (FIG. 9).

[0104] For the memory macro cell M3, the column address (CA) 64 isshifted by 32 to allocate the column addresses 96 to 111 by the columnconfiguration-changing circuit 83 (FIG. 9).

[0105]FIG. 11 shows a circuit diagram used for column address shiftingfor, for example, the memory macro cell M2 from FIG. 9 to FIG. 10A.

[0106] Shown in FIG. 11 are a memory call array 112 of two 1 K rowscorresponding to the memory macro cell M2 (FIG. 9), and a columnconfiguration-switching circuit 110 and a column decoder 111 for thememory cell array 112.

[0107] The column configuration-switching circuit 110 has multipliers110 a to 110 h and their corresponding inverters, controlled by aconfiguration-switching signal CONF, like those shown in FIGS. 3 and 4.

[0108] For a test-configuration A shown in FIG. 10A, the columnaddresses CA [4:6] are converted into complementary internal columnaddresses CAINTAt [4:6] and CAINTAc [4:6] and supplied to the columndecoder 111.

[0109] For a regular-configuration B shown in FIG. 10B, the columnaddress CA [4] is converted into complementary internal column addressesCAINTAt [4] and CAINTAc [4] and supplied to the column decoder 111.

[0110] A decode output for the test-configuration A and that for theregular-configuration B are ORed by the column decoder 111. AND gates8-10 a and 8-11 a constitute a decoder for the test-configuration A. Theoutputs of the AND gates 8-10 a and 8-11 a are fed to OR gates 8-10 band 8-11 b, respectively. There is no specific decoder for theregular-configuration B because of one address. Internal columnaddresses are directly supplied to the OR gates 8-10 b and 8-11 b.

[0111] In detail, the internal column address s CAINTAt [6], CAINTAc [5]and CAINTAt [4] are supplied t the AND gates 8-10 a that produces ahigh-level output when all the input addresses are high.

[0112] The output of the AND gates 8-10 a and an internal column addressCAINTBt [4] are supplied to the OR gate 8-10 b that produces a selectionsignal 1KC_Sel [1] for selecting one of the 1 K-row.

[0113] On the other hand, internal column addresses CAINTAt [6], CAINTAc[5] and CAINTAc [4] are supplied to the AND gates 8-11 a that produces ahigh-level output when all the input addresses are high.

[0114] The output of the AND gates 8-11 a and an internal column addressCAINTBc [4] are supplied to the OR gate 8-11 b that produces a selectionsignal 1KC_Sel [0] for selecting the other 1 K-row.

[0115] A “0”-configuration indication signal CONF forces themultiplexers 110 g and 110 h to connect the first input terminal “1”)(Vss) to the output terminal “O”. This brings the internal columnaddresses CAINTBt [4] and CAINTBc [4] into a low level (non-activestate), thus no 1 K-row being selected in response to these addresses.

[0116] On the other hand, the “0”-configuration indication signal CONFallows the multiplexers 110 a to 110 f to produce high-level internalcolumn addresses CAINTAt [4:6] and low-level internal column addressesCAINTAc [4:6] in response to the column addresses CA [4:6].

[0117] In detail, a high-level column address CA [6] and a low-levelcolumn address CA [5] activate either one of the selection signals1KC_Sel [0:1] in accordance with the value of column address CA [4] toactivate either one of the two 1 K-rows in the memory cell array 112,which means addresses 64 to 95 are allocated to the column address spaceof the memory macro cell M2, as shown in FIG. 10A.

[0118] On the contrary, a “1”-configuration indication signal CONFforces all the internal column addresses CAINTAt [4:6] and CAINTAc [4:6]to be low without respect to input column addresses.

[0119] The “1”-configuration indication signal CONF allows the internalcolumn addresses CAINTBt [4] and CAINTBc [4] to be active in accordancewith th input column address CA [4]. This activates either one of theselection signals 1KC_Sel [0:1] to activate either one of the two 1K-rows in the memory cell array 112, which means addresses 0 to 31 areallocated to the column address of the memory macro cell M2, as shown inFIG. 10B.

[0120] According to this embodiment, column address allocation asdisclosed above offers a test with increase in address for successiveaccess to the memory macro cells M1 to 93 as if they constitute one (1k-row×112-column) memory macro cell. A period of such a test is veryshort compared to tests in which the memory macro cell M1 to M3 areaccessed separately.

[0121]FIG. 9 illustrates different types (capacity) of the memory macrocells M1 to M3. The present invention is, however, is applicable to thesame type (capacity) of the memory macro cells.

[0122] Moreover, FIG. 10A illustrates successive address allocation,such as, from 0 to 63, 64 to 95 and 96 to 111. Not only that, thepresent invention achieves un-successive address allocation, such as,from 0 to 63, 64 to 84 and 96 to 111.

[0123]FIG. 12 shows a modification to the configuration-switchingcircuit for column-address shifting, such as, illustrated in FIG. 10A,for the macro memory cell M2 shown in FIG. 9.

[0124] In FIG. 12, a start address stored in a start address register121 is supplied to a subtracter 122 and subtracted from input columnaddresses CA [0:6]. The output of the subtracter 122 and the columnaddresses CA [0:6] are supplied to a multiplier 123, either one of thembeing output as internal addresses [0:6] according to aconfiguration-switching signal CONF “0” or “1”.

[0125] A “1”-configuration-switching signal CONF allows the input columnaddresses CA [0:6] as internal addresses [0:6] to allocate addresses 0to 31 in a regular address space for the memory macro cell 42 asillustrated in FIG. 10B

[0126] On the other hand, a “0”-configuration-switching signal CONFallocates the values, such as, 64 to 95, as illustrated in FIG. 1A,shifted from the start address stored in the start address register 121in a column address space for the memory macro cell M2.

[0127] As disclosed, this modification also achieves selection betweenth test-configuration A and the regular-configuration B.

[0128] Disclosed so far is change in configuration of memory macro cellfor reduction in cost of test. Not only limited to this, however, thepresent invention also achieves change in configuration of memory macrocells mounted on a memory-logic LSI for specific access speed and powerconsumption, for example, change between the (1 k-row×4k-column)-configuration shown in FIG. 6A and the (2 k-row×2 k-column)-configuration shown in FIG. 8A according to a configuration-switchingsignal CONF.

[0129] In detail, for example, the memory macro cell is changed to the(1 k-row×4 k-column)-configuration according to a“0”-configuration-switching signal CONF. It is then changed to the (2k-row×2 k-column)-configuration according to a“1”-configuration-switching signal CONF.

[0130] The former configuration has a high access speed because of manycolumns, however, consumes much power. Contrary to this, the latterconfiguration, has a low access speed, however, consumes little power.

[0131] As disclosed, the present invention offers a variety of usage ofmemory-logic LSIs by changing or selecting configuration of memory macrocells as one of performance specifications.

[0132] As disclosed above, the present invention offers memory macrocells that are changeable in configuration. Reduction in cost of test isthus achieved by changing memory macro cells to be used for differentpurposes or different types of products into the same configuration.

[0133] Moreover, according to the present invention, a plurality ofmemory macro cells mounted on a one-chip LSI are changed into differentconfigurations, thus achieving the same test to the cells by allocatinga series of address space to them.

What is claimed is:
 1. A semiconductor device comprising: at least onelogic circuit; and at least one memory macro cell having a plurality ofmemory cell array blocks each composed of a plurality of memory cells,wherein addresses for designating the memory cell array blocks in testare selected among external addresses by a switching signal.
 2. Asemiconductor device comprising; at least one logic circuit; and aplurality of memory macro cells having a plurality of memory cell arrayblocks each composed of a plurality of memory cells, wherein at leastone of the memory macro cells is switched in configuration as having thesame length of rows or columns between the memory cell array blocks intest, the configuration being different from a configuration of row andcolumn for a regular operation.
 3. The semiconductor device according toclaim 2, wherein at least one of the memory macro cells is switched inconfiguration as having the same length of rows corresponding to onememory cell array block in the test.
 4. The semiconductor deviceaccording to claim 2, wherein addresses are allocated to rows or columnsnot being subjected to the configuration switching to the same length sothat the same address is not allocated between the memory macro cells.5. The semiconductor device according to claim 4, wherein successiveaddresses are allocated to the rows or the columns not being subjectedto the configuration switching to the same length, for at least twomemory macro cells.
 6. A semiconductor device having a plurality ofmemory macro cells, each memory macro cell comprising: a plurality ofmemory cell array blocks each having a plurality of memory cells,composed of rows and columns; a decoder configured to decode a row or acolumn address signal to select at least one memory cell located on arow or a column corresponding to the decoded address signal; and aswitching circuit configured to convert the row or the column addresssignal in response to a switching signal and supply the converted signalto the decoder to set address spaces having the same length of rows orcolumns between the plurality of memory cells.
 7. The semiconductordevice according to claim 6, wherein the switching circuit activates allof the memory cell blocks or a part of the blocks.
 8. The semiconductordevice according to claim 7, wherein the switching circuit includes: aplurality of first logic circuits each configured to receive the row orthe column address signal and a predetermined voltage and output eitherthe address signal or the voltage in response to the switching signal;and the decoder includes: a plurality of second logic circuitsconfigured to output logical multiplication of address signals orvoltages output by the first logic circuits.
 9. The semiconductor deviceaccording to claim 7, wherein the decoder includes a plurality ofconstituents each configured to select at least one memory cell in thepart of the memory cell array blocks.
 10. The semiconductor deviceaccording to claim 9, wherein the decoder is a row decoder.
 11. Thesemiconductor device according to claim 6, wherein the switching circuitincludes: a first selector configured to receive a column address signalindicating a first column address for use of the memory macro cellsindependently in response to the switching signal to select one of therows; and a second selector configured to receive a column addresssignal indicating a second column address for use of two or more of thememory macro cells in response to the switching signal, the secondcolumn address being not shared by at least the two memory macro cells,to select one of the rows, and the decoder includes: a logic circuitconfigured to take a logical sum of the outputs of the first and secondselectors.
 12. The semiconductor device according to claim 11, whereinthe first selector includes a plurality of logic circuits, eachconfigured to receive the column address signal and a predeterminedvoltage and output either the address signal or the voltage in responseto the switching signal.
 13. The semiconductor device according to claim11, wherein column address signals for two or more of the memory macrocells indicate successive column addresses for at least two memory macrocells.
 14. The semiconductor device according to claim 12, wherein thesecond selector includes a plurality of logic circuits, each configuredto receive the column address signal and a predetermined voltage andoutput either the address signal or the voltage in response to theswitching signal.
 15. The semiconductor device according to claim 12,wherein the second selector includes: an address register configured to,store a start address; a subtracter configured to subtracts the startaddress from a column address indicated by the column address signal;and a selector configured to select either the column addresses or theoutput of the subtracter as the second column address in response to theswitching signal.
 16. A method of testing a semiconductor device havingat least one logic circuit and at least one memory macro cell having aplurality of memory cell array blocks each composed of a plurality ofmemory cells, comprising the step of selecting addresses for designatingthe memory cell array blocks among external addresses by a switchingsignal.
 17. A method of testing a semiconductor device having at leastone logic circuit and a plurality of memory macro cells having aplurality of memory cell array blocks each composed of a plurality ofmemory cells comprising the step of switching at least one of the memorymacro cells in configuration as having the same length of rows orcolumns between the memory macro cells, the configuration beingdifferent from a configuration of row and column for a regularoperation.
 18. The method according to claim 17, wherein at least one ofthe memory macro cells are switched in configuration as having the samelength of rows corresponding to one memory cell array block length. 19.The method according to claim 17 further comprising the step ofallocating addresses to rows or columns not being subjected to theconfiguration switching to the same length so that the same address isnot allocated between the memory macro cells.
 20. The method accordingto claim 19, wherein successive addresses are allocated to the rows orthe columns not being subjected to the configuration switching to thesame length for at least two successive memory macro cells.